The present invention relates to a majority circuit to determine a majority of the level of a digital signal of a plurality of serial bits.
In the field of digital circuits, majority circuits to determine a majority of the level ("1" level or "0" level) of a digital signal of a plurality of serial bits are widely used.
FIG. 1 shows an example of conventional majority circuits. The majority circuit receives a serial digital signal D.sub.in of three bits and determines a majority logic of the signal. The majority circuit comprises one-bit shift registers 1 to 3 which are cascade connected and a gate circuit 4. Gate circuit 4 comprises NAND gates 5 to 8.
Three-bit input serial data D.sub.in is inputted shift register 1 of the first stage. Each of shift registers 1 to 3 shifts the input data by one bit synchronously with a clock signal. Output signals of shift registers 1 to 3 are inputted to NAND gates 5 to 7 in gate circuit 4. Output signals of NAND gates 5 to 7 are inputted to NAND gate 8 and an output signal of NAND gate 8 becomes a majority output D.sub.out.
In the majority circuit of FIG. 1, the one-bit shift registers equal to the number of input serial bits are cascade connected to constitute a counter circuit, the input serial bits are converted to parallel bits, and the parallel bit data is inputted to gate circuit 4, thereby obtaining a majority output.
The circuit arrangement of FIG. 1 requires the 1-bit shift registers equal to the number of input bits. Therefore, as the number "n" of input bits increases, the number of shift registers required also increases. Further, the number of NAND gates constituting gate circuit 4 also increases.
For example, a majority circuit for seven input bits constituted using the circuit arrangement shown in FIG. 1 has a circuit arrangement as shown in FIG. 2. As shown in FIG. 2, seven shift registers 11 to 17 are needed as shift registers constituting a counter circuit, and thirty-five 4-input NAND gates 19 and one 35-input NAND gate 20 are needed as gate logic elements constituting a gate circuit. As mentioned above, in the conventional circuit arrangement as shown in FIG. 1, the number of logic elements required remarkably increases with an increase in number of input bits. Moreover, the wirings among those elements also become complicated in association with the increase in number of elements. Consequently, there is a problem such that the size of the required chip enlarges.